1. Field of the Invention
The present invention relates to an electrostatic discharge protection device. In particular, the invention relates to an electrostatic discharge protection device for discharging a current flowing due to static charges impressed to an external terminal of a semiconductor device through an electrostatic discharge protection element.
2. Description of Related Art
If static charges are impressed to a terminal of a semiconductor device, an abnormal current (hereinafter referred to as “surge current”) flows through a circuit due to the static charges. If the surge current is generated, there is a fear that an internal circuit is broken down. The breakdown resulting from the electrostatic charges is hereinafter referred to as “electrostatic breakdown”.
To prevent the electrostatic breakdown, general semiconductor devices incorporate an electrostatic discharge protection device. Japanese Unexamined Patent Application Publication No. 2003-203985 discloses an example of an electrostatic discharge protection device.
FIG. 25 is a circuit diagram of an electrostatic discharge protection device 100 as disclosed in Japanese Unexamined Patent Application Publication No. 2003-203985. As shown in FIG. 25, the electrostatic discharge protection device 100 of the related art includes a PNP transistor 101, an NPN transistor 102, an diode-connected NMOS transistor 104, an input/output terminal (I/O terminal), a power supply terminal (VDD terminal), and a ground terminal (GND terminal). The I/O terminal is an input/output terminal of a semiconductor device. The terminal is connected with an internal circuit. The PNP transistor 101 has a collector connected with a GND terminal through a resistor Rpw, an emitter connected with the I/O terminal, and a base connected with a VDD terminal through a resistor Rnw. The NPN transistor 102 has a collector connected with the base of the PNP transistor 101, an emitter connected with the GND terminal, and a base connected with the collector of the PNP transistor.
The NMOS transistor 104 has a source connected with the GND terminal, a drain connected with the VDD terminal, and a gate connected with the source. That is, in the electrostatic discharge protection device of the related art, the PNP transistor 101 and the NPN transistor 102 constitute a thyristor.
Description is made of how the electrostatic discharge protection device 100 protects an internal circuit against breakdown. Electrostatic charges are impressed to the I/O terminal. On the assumption that a potential level of the VDD terminal is used as the reference, if positive electrostatic charges are impressed (VDD+ impressed), a parasitic diode of the PNP transistor 101 is forward-biased, and then a surge current flows into the VDD terminal.
If positive electrostatic charges are impressed based on the potential level of the GND terminal (GND+ impressed), the breakdown of the diode-connected NMOS transistor occurs, and the thyristor is turned on. As a result, a surge current flows into the GND terminal.
The electrostatic discharge protection device 100 protects the internal circuit from breakdown by discharging the surge current through the above path.
However, in the electrostatic discharge protection device 100 of the related art, it is difficult to protect the circuit if negative electrostatic charges are impressed. In addition, if a breakdown path at the PN junction of the transistor is used as the surge current path, there is a fear that enough current cannot flow and the semiconductor device is broken down.